The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a lightly doped drain (LDD) region of a field effect transistor, and more particularly to the manufacture of a complementary metal oxide silicon field effect (CMOS) transistor, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as bipolar complementary metal oxide silicon field effect (BiCMOS) transistors, among others.
Industry utilizes or has proposed several techniques for the manufacture of an MOS integrated circuit device, and in particularly an LDD region for such device. For example a typical technique to form an N type channel MOS device often includes a step of forming a gate region overlying a P type well region. The P type well region is defined in a semiconductor substrate. A first implant step using the gate region as a mask forms first source and drain regions at low N type concentrations, typically known as LDD regions. The technique then forms sidewall spacer structures on the gate edges. A second implant step using the gate region and sidewall spacer structures as a mask provides higher concentrations of N type ions into the source and drain regions, thereby forming the MOS device having the LDD structure.
A limitation with the typical N type channel MOS device with LDD structure includes hot electron injection effects when some electrons inject into the gate oxide beneath sidewall spacers. The typical N- type channel MOS (NMOS) LDD structure often locates more of the N- type region outside the gate electrode, that is, a greater portion of the N- type region is underneath the sidewall spacers, rather than directly beneath the gate electrode. When voltage at the gate electrode turns the device on, hot electrons inject into sidewall spacer region, often increasing the resistance in the N- type regions directly beneath such sidewall spacers. This tends to cause the N- type regions underneath the sidewall spacers to "pinch off" by way of the higher resistance in the N- type region.
Another limitation exists by the use of the LDD structure in a typical P type channel depletion mode metal oxide silicon (PMOS) field effect device. The PMOS device uses a P type buried channel structure and P type source and drain regions. As the channel length becomes shorter in the typical PMOS device, short channel effects such as punchthrough and others tend to occur. Punchthrough typically shorts the PMOS source and drain regions together, thereby rendering the device partially inoperative. In addition, when the source and drain regions become implanted with an impurity having a high diffusion co-efficient such as boron or the like, lateral diffusion of such impurities also tends to be another cause of the punchthrough phenomenon.
A further limitation in the fabrication of LDD structures, and particularly for CMOS type devices is the high quantity of main mask steps, typically at least five to merely form both NMOS and PMOS devices up to the LDD structures. Each masking step often increases work-in-process time for the semiconductor product. An increase in work-in-process time generally corresponds to a longer product turn-around-time, typically measured from wafer start to final test. Longer product turn-around-time is typically an undesirable consequence for the manufacture of CMOS devices and often translates into higher costs in manufacture, and the like.
Still further, it is often desirable to reduce defects in the wafer introduced during its processing. Wafer fabrication processes such as masking, exposing, developing, etching, and others typically introduce particles into the integrated circuit. These particles often contribute to the amount of defective integrated circuit chips. Generally, more masks used in a semiconductor process tends to contribute to more defective integrated circuit chips. For example, a conventional CMOS process relies on at least five separate masks to form the LDD and source/drain regions for NMOS and PMOS devices. As industry attempts to increase the yield of good integrated circuit chips on a wafer, it is often desirable to reduce the number of masks (or masking steps) used during wafer manufacture.
From the above it is seen that a method of fabricating semiconductor LDD structure that is easy, reliable, faster, cost effective, and is often desired.